This white paper describes the JasperGold Property Synthesis Apps, members of a family of interoperable, application-specific formal verification solutions that addresses verification challenges ...

Imagine a world where the chips powering your smartphones, computers, and even cars are designed and tested with unparalleled precision and speed. Welcome to the realm of Very Large Scale Integration ...

Chip designs today have more functionality, more black-boxed intellectual property (IP) and shorter tape-out schedules. However, they require even more design verification than in the past, which ...

According to industry pundits, FPGAs take forever to compile and have internal timing problems. ASICs, on the other hand, are power-hungry and require longer development time. When it comes to ...

Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has announced the latest release of the Riviera-PRO, providing support for system ...

Industrial simulation and emulation are powerful but still underemployed techniques for designing, developing, and testing better automation solutions and machines. When used as a central part of a ...

Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for Cadence; Russ ...

I recently attended an invited talk by a senior manager of a design group within a large networking company. He described the group’s verification flow and it quickly became obvious that hardware ...

Grenoble, France, March 20th, 2001 - DOLPHIN Integration SA and RAISONANCE SA have launched a visionary innovation for adapting traditional Microcontroller Development techniques to the age of Silicon ...