EDN

Clock-distribution ICs provide up to 20 outputs

Hillsboro, Ore.&#8212Lattice Semiconductor's ispClock5316 and ispClock5320 clock distribution ICs, extensions to the company's ispClock5300S family of in-system programmable, zero-delay, single-ended ...
Hackaday

clock distribution

[Oleg Kutkov] decided to build a wideband SDR – for satellite communication research and monitoring, you know, the usual. He decided on a battery of HackRF boards – entire eight of them, in fact. Two ...
Hackaday

Neat Ring Clock Relies On Addressable LEDs

[WhiskeyTangoHotel] wanted to build an LED clock after seeing some great designs online. They elected to go after a ring clock design, based around the ever-popular WS2812B addressable LEDs. The core ...
EDN

Buffers minimize jitter in clock distribution, differential signal lines

High performance clock buffers – those without phase-locked loops (PLLs) – are often used in communications designs for duplication, distribution and fanout of clock signals. Sensitivity to long-term ...
Electronic Design

Understand, Measure, And Optimize Clock Distribution Additive Jitter To Achieve Best Performance

High-speed communications require system designers to optimize clocking performance while adhering to both performance and cost-budget requirements. When selecting an optimal clock, the developer must ...
Electronic Design

PCI Express Clock Generators, Buffers Prepare for Next Generation

PCIe has been around since 2004. It’s a high-speed serial computer expansion bus specification that replaces older PCI and PCI-X standards. PCIe currently supports the Generation 4 specification. In ...