Design-Reuse

100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process

100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process View 100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; ...
EDN

PCIe Gen2 clock buffers offer ultra-low jitter

San Jose, Calif. — Pericom Semiconductor Corp. has announced production availability of high-performance, zero-delay clock buffer products that are designed to provide reference clocks for the PCIe ...
Electronic Design

PCIe Clock Buffers Support 5 Gb/s Serial Connectivity

The company's second-generation family of PCI Express clock buffers provides reference clocks for serial connectivity at 5 Gb/s and meets the reference clock requirements of fully buffered DIMMs. The ...
EDN

Pericom Announces PCI Express® Gen2 Clock Buffer Family

SAN JOSE, Calif. – June 25, 2007 – Pericom Semiconductor Corporation (NASDAQ: PSEM), a worldwide preferred supplier of PCI Express (PCIe) technology used for high-speed switching, timing, bridging and ...
Electronic Design

PCI Express Clock Generators, Buffers Prepare for Next Generation

PCIe has been around since 2004. It’s a high-speed serial computer expansion bus specification that replaces older PCI and PCI-X standards. PCIe currently supports the Generation 4 specification. In ...
Design-Reuse

PCI Express Differential Buffer IP, Single - Ended, UMC 90nm SP process

100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process.
Business Wire

PCI Express Clock Jitter Measurement Tool from Silicon Labs Simplifies Timing Design

AUSTIN, Texas--(BUSINESS WIRE)--Silicon Labs (NASDAQ: SLAB) has introduced a free software tool that enables engineers to quickly and easily measure PCI Express® (PCIe®) clock jitter from an ...